1. Field
This disclosure relates generally to data processing, and more specifically, to a scannable flip-flop in low power operating modes, including scan-shift mode, in a data processing system.
2. Related Art
Many integrated circuits include a plurality of flip-flops that are used to provide logic operations during normal operating modes and for testing the integrated circuit during a scan-shift mode. During testing, the flip-flops are formed in a scan-chain and test data is scanned through the scan-chain. When the integrated circuit is operating in scan-shift mode, the system clock runs at a slower speed while data is clocked though the flip-flops. In scan-shift mode, all of the flip-flops operate at the same time causing a large current flow thus increased demand on the power supply and increased power consumption. The large current can be reduced by staggering the operation of the flip-flops. However, staggering the operation significantly increases the amount of time required to complete the scan testing operation. Also, there may be a problem with “hold violations” during scanning because clock signals provided to subsequent flip-flops in the chain are delayed from a beginning flip-flop and the scan data is running faster than the delayed clock.
Therefore, a need exists for a scan-shift operating mode with lower power consumption and a reduced number of hold violations.